Authors with * are students under my supervision.
[J11] I Bow, N Bete, F Saqib, W Che, C Patel, R Robucci, C Chan, J Plusquellic, “Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity”, Cryptography vol. 4, no. 2, 2020.
[J10] J Calhoun, C Minwalla, C Helmich, F Saqib, W. Che, J Plusquellic, “Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash),” Cryptography, vol. 3, no. 3, 2019.
[J9] W. Che, F. Saqib, J. Plusquellic, “Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 4, pp. 733-743, April 2018. (ieeexplore link)
[J8] D. Owen Jr., D. Heeger, C. Chan, W. Che, F. Saqib, M. Areno and J. Plusquellic, “An Autonomous, Self-Authenticating and Self-Contained Secure Boot Process for FPGAs”, Cryptography (MDPI), vol. 2, no. 3, 2018. (PDF)
[J7] W. Che, V. K. Kajuluri, F. Saqib, J. Plusquellic, “Leveraging Distributions in Physical Unclonable Functions,” Cryptography, vol. 1, no. 3, 2017. (PDF)
[J6] W. Che, V. K. Kajuluri, M. Martin, F. Saqib, J. Plusquellic, “Analysis of Entropy in a Hardware-Embedded Delay PUF,” Cryptography, vol. 1, no. 1, 2017. (PDF)
[J5] W. Che, M. Martin, G. Pocklassery, V. K. Kajuluri, F. Saqib, J. Plusquellic, “A Privacy-preserving, Mutual PUF-Based Authentication Protocol,” Cryptography, vol. 1, no. 1, 2016. (PDF)
[J4] W. Che, Y. Lin, A. Pan, J. Zhang, “A Robust Hierarchical FSM Structure for Active IC Metering,” Information Technology Journal, vol. 12, no. 6, pp. 1107-1115, 2013.
[J3] A. Pan, Y. Lin, W. Che, Z. You, Y. Liu, J. Li, “A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design,” IEICE Electronic Express, vol. 10, no. 19, pp. 1-11, 2013.
[J2] J Zhang, Y Lin, W. Che, Q Wu, Y Lu, K Zhao, “Efficient verification of IP watermarks in FPGA designs through lookup table content extracting,” IEICE Electronics Express, vol. 9, no. 22, pp. 1735-1741, 2012.
[J1] J Zhang, Y Lin, Q Wu, W. Che, “Watermarking FPGA Bitfile for Intellectual Property Protection,” Radioengineering, vol. 21, no. 2, pp. 764-771, 2012.
[C8] R. Valles-Novo*, A. Martinez-Sanchez* and W. Che, “Boosting Entropy and Enhancing Reliability for Physically Unclonable Functions”, accepted as full paper by IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST) 2020. (Acceptance rate: 30%)
[C7] W. Che, M. Martinez-Ramon, F. Saqib, J. Plusquellic, “Delay Model and Machine Learning Exploration of a Hardware-Embedded Delay PUF,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018, pp. 153-158. (PDF)
[C6] G. Pocklassery, W. Che, F. Saqib, M. Areno and J. Plusquellic, “Self-Authenticating Secure Boot for FPGAs,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018, pp. 221-226. (PDF)
[C5] A. S. Siddiqui, C.-C. Lee, W. Che, J. Plusquellic and F. Saqib, “Secure Intra-Vehicular Communication over CANFD”, AsianHOST, 2017, pp. 97-102. (PDF)
[C4] W. Che, F. Saqib, J. Plusquellic, “PUF-based authentication”, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), Austin, TX, USA, 2015, pp. 337–344. (PDF)
[C3] W. Che, J. Plusquellic, S. Bhunia, “A Non-volatile Memory Based Physically Unclonable Function without Helper Data”, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), Nov. 2014, pp. 148–153. (PDF)
[C2] J Zhang, Y Lin, Y Lyu, RCC Cheung, W. Che, Q Zhou, J Bian, “Binding hardware IPs to specific FPGA device via inter-twining the PUF response with the FSM of sequential circuits,” In Proc. 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, USA, 2013, pp. 227.
[C1] J Zhang, Y Lin, Y Lyu, G Qu, RCC Cheung, W. Che, Q Zhou, J Bian “FPGA IP protection by binding finite state machine to physical unclonable function,” in Proc. 23rd Int. Conf. Field Program. Logic Appl. (FPL), Porto, Portugal, 2013, pp. 1–4.